Cypress Semiconductor /psoc63 /SAR /INTR_MASKED

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Interpret as INTR_MASKED

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EOS_MASKED)EOS_MASKED 0 (OVERFLOW_MASKED)OVERFLOW_MASKED 0 (FW_COLLISION_MASKED)FW_COLLISION_MASKED 0 (DSI_COLLISION_MASKED)DSI_COLLISION_MASKED 0 (INJ_EOC_MASKED)INJ_EOC_MASKED 0 (INJ_SATURATE_MASKED)INJ_SATURATE_MASKED 0 (INJ_RANGE_MASKED)INJ_RANGE_MASKED 0 (INJ_COLLISION_MASKED)INJ_COLLISION_MASKED

Description

Interrupt masked request register

Fields

EOS_MASKED

Logical and of corresponding request and mask bits.

OVERFLOW_MASKED

Logical and of corresponding request and mask bits.

FW_COLLISION_MASKED

Logical and of corresponding request and mask bits.

DSI_COLLISION_MASKED

Logical and of corresponding request and mask bits.

INJ_EOC_MASKED

Logical and of corresponding request and mask bits.

INJ_SATURATE_MASKED

Logical and of corresponding request and mask bits.

INJ_RANGE_MASKED

Logical and of corresponding request and mask bits.

INJ_COLLISION_MASKED

Logical and of corresponding request and mask bits.

Links

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